2ED24427N01FXUMA1
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Datasheet
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Samples
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- Channels
- 2
- I(lim,min)/Ch
- 10 A
- Mounting
- SMD
- Diagnostics
- NO
- T(j,max)
- 150 °C
- I(lim,max)/Ch
- -10 A
- V(in,min)
- 12.5 V
- V(in,max)
- 24 V
- t(on)
- 0.04 µS
- t(off)
- 0.055 µS
- OL Detection
- NO
- Automotive
- NO
- Package
- DSO-8
- RoHS Status
- RoHS-conform
- Packaging
- REEL
- Supplier Part
- SP005349592
- ECCN
- EAR99
- Customs Tariff No.
- 85423990000
- Country
- China
- ABC-Code
- A
- Supplier Lead time
- 100 weeks
24 V dual-channel low-side gate driver with high current for driving large power switches
EiceDRIVER™ 24 V dual-channel low-side non-inverting gate driver for MOSFETs or IGBTs with typical 10 A source and sink currents in a DSO-8 package with thermally efficient, exposed power pad. 2ED24427N01F enables higher power and faster switching frequencies in multiple applications with a reduced PCB footprint and increased reliability by simplifying high power density system design.
The 2ED24427N01F is a low-voltage, power MOSFET and IGBT non-inverting gate driver. Proprietary latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output. The output driver features a current buffer stage. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays between two channels are matched. Internal VCC circuitry provides under voltage lockout protection that holds output low until VCC supply voltage is within operating range.
Summary of Features
- 10 A sink and 10 A source driver capability (typical)
- 11.5 V under voltage lockout
- 24 V maximum supply voltage
- Enable function
- CMOS Schmitt-triggered inputs
- Output in phase with input
- 3.3 V, 5 V and 15 V input logic compatible
- PSOIC-8 package with thermal pad
- 2 kV HBM ESD
Benefits
- Large driving capability for high power or paralleled MOSFETs and IGBTs or modules such as EasyPACK™ or EconoPACK™
- Thermally efficient PDSO-8 package increased reliability and overall full load system efficiency
- System cost reduction possible by paralleling more than one switch per channel (e.g. in synchronous rectification)
- System cost and size reduction possible by reducing the number of lower current (e.g. 5 A) low-side gate drivers needed in various power electronic paralleling applications
- Fast EV charging
- Industrial motor drives and controls
- Power Management (SMPS) - Reference Design
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